Kategori: Uluslararası Bildiriler

In this study, wavelet fuzzy system (WFS) together with its PSO-based learning is hardware implemented on FPGA. Floating point number format is used for the implementation considering its precision and dynamics. Although floating point numbers consume more hardware source than the other number format, WFS implementation has been achieved with only 10% hardware sources. A mathematical approximation for implementing of wavelet membership functions has been proposed and exploited. Proposed hardware implementation method has been experimentally inspected on a benchmark system identification problem. Obtained results show that implemented WFS has carried out good performance not only training data but also tested data on the system identification problem.

In this study, a hardware solution for car plate detection problem is proposed based on softcomputing techniques, namely the genetic algorithm and neural networks which are implemented on Programmable Field Gate Array (FPGA). The proposed plate detection requires a successful integration of image processing and pattern classifier algorithms, which impose a high computation load, such as edge detection, statistical bit-wise feature extraction, neural networks and genetic algorithm. In literature, software based approaches to this problem have already been proposed. In this study, however, a hardware based solution is provided by implementing feature extraction, genetic algorithm and neural networks on FPGA.

The FPGAs (Field Programmable Gate Arrays) approach for neural network implementation provides flexibility in programmable systems. For the neural based instrument prototype in real time application, conventional specific VLSI neural chip design suffers from the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than that of the VLSI design. This paper presents a novel fully parallel hardware implementations of neural network for EXOR benchmark problem using Xilinx FPGA. The validity of this approach is demonstrated by application to EXOR problem. The design is tested on an FPGA demo board.

This article explains implementing of Fast Fourier (FFT) and Inverse Fast Fourier Transform algorithms(IFFT) in FPGA. The reason of designing the study on FPGA base is that FPGAs are able to rearrange of logical blocks and moreover, mathematical algorithms can confirm faster by means of parallel data processing. For operating these algorithms, it is used the family of Xilinx Virtex2P xc2vp30fg676-7 FPGA device as a hardware. In programming the hardware and writing codes, VHDL is used. The results show that FFT and IFFT algorithms result in 0.6 μs and 0.72 μs cycle time respectively.